This invention relates generally to the field of reduced instruction set computing, and more specifically to the field of referencing registers in a compressed instruction set.
Reduced instruction set computer (RISC) architectures provide several advantages for programmable processors over traditional complex instruction set (CISC) architecture such as reducing complexity and increasing the speed of operations. However, RISC architectures suffer at least one drawback. The instruction density after compilation (bytes of object code) is often larger than the same program would be after compilation for a CISC architecture. This problem becomes more significant when incorporating RISC architectures, together with their instruction caches, into system-on-chip (SoC) designs. The added cost of larger on-chip memories can pose a serious problem in these cost-sensitive designs. In fact, the code sizes of 32-bit RISC instruction sets for DSP applications compares are often larger than those achieved by older DSP architectures with specialized 16-bit instruction sets.
The MIPS(copyright) RISC architecture uses a standard 32-bit MIPS instruction set together with the MIPS 16 xe2x80x9cApplication Specific Extension,xe2x80x9d an alternative 16-bit instruction set to improve code density. Programs can include sections of contiguous instructions encoded with MIPS 16 and sections of contiguous instructions encoded with 32-bit MIPS instructions. Shortening the instructions from 32-bits to 16-bits required removing some opcodes, shortening the immediate and displacement fields and supporting a smaller register set. Each of these changes results in potential problems that need to be addressed.
The absent opcodes in MIPS 16 are rarely used in application code (as opposed to kernel code) and have little effect on overall code density. The problem of shortened immediate and displacement fields is mitigated by the xe2x80x9cEXTENDxe2x80x9d opcode, which allows full size fields to be provided within MIPS16 at the cost of two 16-bit MIPS16 instructions. Two instructions are used to provide space for the full immediate or displacement values. This is more efficient than switching modes to 32-bit MIPS instructions to execute an instruction with larger immediate or displacement.
One response to the problem of having a smaller register set addressable within MIPS16, is the MIPS16 MOVE instruction, which allows the full register set to be accessed within MIPS16. The 32-bit MIPS instruction allows for addressing thirty-two registers using a 5-bit field. The 16-bit instructions allow for addressing a maximum of 8 registers using a 3-bit field. The MOVE instruction provides access to the other 24 registers by moving data to one of eight MIPS16 registers before the operation is performed. Resultant data may then be moved from one of the eight registers to one of the other twenty-four registers. This requires not only moving data from, for example, register 22 to register 2, but also requires storing the register 2 data somewhere so that the register 2 data may be restored after the operation is complete.
Consider the following MIPS-I instruction: add r20, r21, r22. This instruction requires adding the contents of r21 and r22 and placing the result in r20. For MIPS16, the worst-case scenario is eight instructions:
Compilers can avoid this inefficiency by restructuring code, but this restructuring may prevent other optimizations.
Therefore, there is a need for addressing additional registers in compressed instruction set systems.
The present invention allows for addressing additional registers in a compressed instruction set by concatenating information in two instructions.
A method consistent with the present invention includes the steps of reading a first instruction, determining whether the first instruction is an extend register instruction, reading a second instruction, and concatenating bits in the first instruction with bits in the second instruction when the first instruction is an extend register instruction.
A processor consistent with the present invention includes a set of registers, each register having an address, instruction storage, and an instruction decoder including structure for reading a first instruction from the instruction storage, structure for determining whether the first instruction is an extend register instruction, structure for reading a second instruction from the instruction storage, and structure for concatenating bits in the first instruction with bits in the second instruction when the first instruction is an extend register instruction.
Another processor consistent with the present invention is configured to perform instructions. The instructions include a first instruction having an opcode identifying an extend register instruction, a first register extension with two bits of data, and a second register extension with two bits of data, and a second instruction having first register address with three bits of data, and second register address with three bits of data.
A computer readable memory consistent with the present invention has an instruction comprising an extend register opcode, a first source register extension, and a destination register extension.
Another computer readable memory consistent with the present invention has an extend register opcode, a first source register extension, and a second source register extension.
Another computer readable memory consistent with the present invention has an extend register opcode, a first source register extension, a second source register extension, and a complete destination register extension.